This invention is directed towards an interface control system and in particular towards systems for controlling the timing relationships of clock signals which control data access through interfaces. This invention is particularly suitable for application in computer systems where high speed central processing units are used to access low speed expansion devices of standard specifications, such as "expansion interfaces".
Computer users frequently desire to have expansion interfaces for specific purposes. For this reason many computer systems have expansion buses for connection to expansion interfaces. Furthermore, in order for the expansion interfaces to be compatible with many computer systems, the expansion interfaces are usually designed to have a standard specification. Such specification includes for example predetermined timing relationships and requirements.
To facilitate communication with expansion interfaces, a standard clock is defined for such interfaces and a standard cycle of the interfaces is defined as a preset number of standard clock cycles, during which the interfaces are accessed. In principle, at the end of a standard cycle, a central processing unit (CPU) may conclude its cycle after completing data access to the interface.
Expansion interfaces of standard specification are usually of low speed. With the advent of higher speed CPU's, the CPU cycles may not end at the end of a standard cycle for such low speed expansion devices. In such event, the computer system employing such CPU's are not entirely compatible with the expansion interfaces. This will not only affect the efficiency of the computer system when such interfaces are employed but may also cause the system to malfunction.
It is therefore desirable to provide an interface control system in which the above described difficulties are alleviated.